Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly relates to a semiconductor device as a target for a wafer test performed using a probe card.
Description of Related Art
When a wafer test on a semiconductor device such as a DRAM (Dynamic Random Access Memory) is to be performed, predetermined potentials and signals are supplied from a tester through a probe card to a plurality of semiconductor devices formed on one wafer. Each of the semiconductor devices is configured to perform a predetermined test operation in response to the potentials and the signals thus supplied. Japanese Patent Application Laid-open No. 2012-99603 discloses an example of a wafer test on a DRAM. Japanese Patent Application Laid-open No. H6-53299 discloses an example of a probe card.
The voltages supplied to a semiconductor device during a wafer test include a power supply potential VDD and a reference potential VREF0. Among these, the reference potential VREF0 is a voltage serving as a reference when the semiconductor device generates various internal potentials, and the reference potential VREF0 itself is an internal potential generated inside of the semiconductor device (see, for example, Japanese Patent Application Laid-open No. 2012-38389). While adjustment is required for the semiconductor device to generate the reference potential VREF0 of a correct value, the adjustment is not finished yet at the wafer test stage. Accordingly, there is a possibility that the reference potential VREF0 of a correct value is not generated and thus the reference potential VREF0 is supplied from a tester.
The probe card mentioned above has first and second power supply terminals that receive the power supply potential VDD and the reference potential VREF0, respectively, from the tester and a plurality of pins. The pins form sets of a predetermined number of pins (pin sets) for the semiconductor devices as test targets, respectively. Each of the pin sets includes a first pin for supplying the power supply potential VDD and a second pin for supplying the reference potential VREF0.
The first pins in the pin sets are connected in parallel to the first power supply terminal. Accordingly, the power supply potential VDD is supplied from the tester to the first pins in common. When the wafer test is to be conducted, the first pins are connected to first pads provided on surfaces of the corresponding semiconductor devices, respectively. Each of the first pads is connected to a power supply line provided throughout the inside of the corresponding semiconductor device and thus the power supply potential VDD can be supplied from the tester to internal circuits of the semiconductor device.
The second pins in the pin sets are connected in parallel to the second power supply terminal. Accordingly, the reference potential VREF0 is supplied from the tester to the second pins in common. The second pins are connected to second pads provided on the surfaces of the corresponding semiconductor devices, respectively, when the wafer test is to be conducted. Each of the second pads is connected to an output end (hereinafter, “first node”) of a reference-potential generation circuit, which is located in the semiconductor device and functions to generate the reference potential VREF0. Therefore, the reference potential VREF0 generated in the semiconductor device normally can be replaced with the reference potential VREF0 supplied from the tester.
The wafer test is conducted on the semiconductor devices as the test targets in turn. For this purpose, a first relay is provided between each of the first pins and the first power supply terminal. When a test on a certain semiconductor device is to be conducted, only the first relay corresponding to the semiconductor device is brought to a connection state and the remaining first relays are brought to a disconnection state. Accordingly, the power supply potential VDD is supplied only to the semiconductor device that is being tested.
A second relay is provided between each of the second pins and the second power supply terminal. The second relays are provided to prevent a situation that, in a semiconductor device to which supply of the power supply potential VDD from the tester is interrupted due to a disconnection state of the first relay, a leak current flows from the first node mentioned above to the reference-potential generation circuit, a current thus flows to the corresponding second pin, and that a current supply capacity of the tester consequently becomes insufficient, whereby a sufficient reference potential VREF0 cannot be supplied to the semiconductor device being tested. The leak current is a current flowing from the first node toward an n-well that forms the body of a P-channel MOS transistor forming the output end of the reference-potential generation circuit. Such a leak current possibly occurs when the power supply potential VDD is not supplied to a source of the P-channel MOS transistor. Because a disconnection state of the second relay stops supply of the reference potential VREF0 to the first node, a flow of a current to the second pin can be prevented.
However, in more recent wafer testing, examination of as many as 500 semiconductor devices needs to be performed in one test and the number of semiconductor devices to be examined in one test will further increase in the future. Therefore, the configuration using the two relays for each semiconductor device as the test target is not preferable in terms of downscaling of the probe card. Accordingly, a semiconductor device that can reduce the number of relays to be mounted on a probe card is demanded.